Bug 599

Summary: Usage of LSB0 in EXTRA pseudo-code
Product: Libre-SOC's first SoC Reporter: Cesar Strauss <cestrauss>
Component: SpecificationAssignee: Luke Kenneth Casson Leighton <lkcl>
Status: RESOLVED FIXED    
Severity: enhancement CC: libre-soc-isa
Priority: ---    
Version: unspecified   
Hardware: PC   
OS: Linux   
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Attachments: Proposed fixes for MSB0 issues in pseudo-code

Description Cesar Strauss 2021-02-15 21:21:25 GMT 
Consider the pseudo-code for register number augmentation:

https://libre-soc.org/openpower/sv/svp64/#index13h1

Accorting to the tables below, it seems that the bit for scalar/vector selection in "spec" is intended to be its MSB.

So, in MSB0 notation, it should be spec[0], not spec[2].

The augmentation bits then are the two less significant, so it should be spec[1:2], not spec[0:1].

In other words:

if extra3_mode:
    spec = EXTRA3
else:
    spec = EXTRA2 << 1 # same as EXTRA3, shifted
if spec[0]: # vector (MSB of spec)
     return (RA << 2) | spec[1:2]
else:         # scalar
     return (spec[1:2] << 5) | RA
Comment 1 Cesar Strauss 2021-02-20 12:08:15 GMT 
Created attachment 126 [details]
Proposed fixes for MSB0 issues in pseudo-code

After a review of SVP64 register remapping documentation, I found these places where LSB0 numbering was being used in pseudo-code. OK to commit?
Comment 2 Luke Kenneth Casson Leighton 2021-02-20 12:16:32 GMT 
Comment on attachment 126 [details]
Proposed fixes for MSB0 issues in pseudo-code

ah ok in the spec?  yes go for it.  i will try not to cry into my tea too much.  ok i'm done.  commit it :)
Comment 3 Cesar Strauss 2021-02-20 14:32:01 GMT 
(In reply to Luke Kenneth Casson Leighton from comment #2)
> ah ok in the spec?  yes go for it.  i will try not to cry into my tea too
> much.  ok i'm done.  commit it :)

Done.