Bug 618

Summary:	add SVP64 predication to ISACaller
Product:	Libre-SOC's first SoC	Reporter:	Luke Kenneth Casson Leighton <lkcl>
Component:	Source Code	Assignee:	Luke Kenneth Casson Leighton <lkcl>
Status:	CONFIRMED ---
Severity:	enhancement	CC:	libre-soc-bugs
Priority:	---
Version:	unspecified
Hardware:	PC
OS:	Linux
URL:	https://libre-soc.org/openpower/sv/implementation/
See Also:	https://bugs.libre-soc.org/show_bug.cgi?id=583 https://bugs.libre-soc.org/show_bug.cgi?id=617
NLnet milestone:	---	total budget (EUR) for completion of task and all subtasks:	0
budget (EUR) for this task, excluding subtasks' budget:	0	parent task for budget allocation:
child tasks for budget allocation:		The table of payments (in EUR) for this task; TOML format:
Bug Depends on:
Bug Blocks:	241

Description Luke Kenneth Casson Leighton 2021-03-17 15:21:57 GMT

both single and twin predication needs adding to ISACaller simulator,
for CR and INT sources.

* INT-based single: done
* CR-based single:  done
* INT-based twin:   TODO
* CR-based twin:    TODO
* Zeroing single:   TODO
* Zeroing twin:     TODO

Comment 1 Luke Kenneth Casson Leighton 2021-03-17 15:23:08 GMT

commit 379cc6df93eec26dae0fc523b18a1996f1e90d97 (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Wed Mar 17 15:20:02 2021 +0000

    add SVP64 INT-style predication to ISACaller

Comment 2 Luke Kenneth Casson Leighton 2021-03-17 20:42:53 GMT

commit 4a62e46f76219b3c02fee379047d8a18df2f22fc (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Wed Mar 17 20:40:49 2021 +0000

    add CR-based predication to ISACaller