Bug 62

Summary:	nmigen-based general-purpose util / data handling / io-control library needed
Product:	Libre-SOC's first SoC	Reporter:	Luke Kenneth Casson Leighton <lkcl>
Component:	Source Code	Assignee:	Luke Kenneth Casson Leighton <lkcl>
Status:	RESOLVED FIXED
Severity:	enhancement	CC:	libre-soc-bugs
Priority:	High
Version:	unspecified
Hardware:	PC
OS:	Linux
NLnet milestone:	NLnet.2019.02.012	total budget (EUR) for completion of task and all subtasks:	4550
budget (EUR) for this task, excluding subtasks' budget:	0	parent task for budget allocation:	191
child tasks for budget allocation:	63 64 68 132	The table of payments (in EUR) for this task; TOML format:
Bug Depends on:	64, 65, 66, 63, 68
Bug Blocks:

Description Luke Kenneth Casson Leighton 2019-04-19 08:50:36 BST

similar to chisel3 util and not quite as generally along the lines
of litex, and augmenting nmigen.lib, a data handling, i/o control,
pipeline-building-block, queues (FIFOs) and general utils library
is needed.

two key pieces of information to decide:

* name of the repo
* name (hierarchy) in python

Subtasks (edit this comment to add, and create sub-bug):

* bug #63 queue (FIFO) with write-through and support for 1-address entries
* bug #65 variable-length IN, variable-length OUT queue
* bug #64 data handling and routing, i/o control and synchronisation
* bug #68 general small utility routines
* bug #66 nmigen Object class needed (python inheritance)
* bug #132 general-purpose nmigen SIMD (Partitioned Signal)

links:

* https://github.com/m-labs/nmigen/tree/master/nmigen/lib
* https://chisel.eecs.berkeley.edu/api/3.0.1/chisel3/util/Queue.html
* https://github.com/freechipsproject/chisel3/tree/src/main/scala/chisel3/util
* https://github.com/enjoy-digital/litex/blob/master/litex/gen/common.py

Comment 1 Luke Kenneth Casson Leighton 2019-05-02 14:30:29 BST

we need a decision on the name of the library and the name of the
git repository.