Bug 622

Summary:	cxxrtl bugs
Product:	Libre-SOC's first SoC	Reporter:	Luke Kenneth Casson Leighton <lkcl>
Component:	Source Code	Assignee:	whitequark
Status:	RESOLVED FIXED
Severity:	enhancement	CC:	libre-soc-bugs
Priority:	Low
Version:	unspecified
Hardware:	PC
OS:	Linux
See Also:	https://bugs.libre-soc.org/show_bug.cgi?id=475 https://bugs.libre-soc.org/show_bug.cgi?id=362
NLnet milestone:	---	total budget (EUR) for completion of task and all subtasks:	0
budget (EUR) for this task, excluding subtasks' budget:	0	parent task for budget allocation:
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Attachments:	repro case 1 repro case 2

Description Luke Kenneth Casson Leighton 2021-04-10 00:53:54 BST

Created attachment 129 [details]
repro case 1

couple of bugs in cxxrtl

ERROR: Assert `cell_module != nullptr && cell_module->wire(conn.first) && conn.second.is_wire()' failed in backends/cxxrtl/cxxrtl_backend.cc:1339.

repro cases:

    https://ftp.libre-soc.org/ls180bug2.v
    https://ftp.libre-soc.org/ls180bug.v

latest yosys master
commit a58571d0fe8971cb7d3a619a31b2c21be6d75bac (HEAD -> master, origin/master, origin/HEAD)

this is *after* the commit
#2724 from whitequark/flatten-rewrite-memwr-memid

Comment 1 Luke Kenneth Casson Leighton 2021-04-10 00:54:13 BST

Created attachment 130 [details]
repro case 2