| Summary: | add SVSRR0 to TRAP pipeline | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Luke Kenneth Casson Leighton <lkcl> |
| Component: | Source Code | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | CONFIRMED --- | ||
| Severity: | enhancement | CC: | libre-soc-bugs |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Linux | ||
| See Also: |
https://bugs.libre-soc.org/show_bug.cgi?id=325 https://bugs.libre-soc.org/show_bug.cgi?id=636 https://bugs.libre-soc.org/show_bug.cgi?id=629 |
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| NLnet milestone: | --- | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
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Description
Luke Kenneth Casson Leighton
2021-05-04 18:06:40 BST
commit 321afe236aa1e44a99a94a774c3e6b412a61e8d9 (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Tue May 4 18:40:35 2021 +0100 add SVSTATE (SVSRR0) to TRAP pipeline involves adding svstate to TrapOutputData regspec, and a corresponding write port to StateRegs, and adding svstate to CompTrapOpSubset |