Bug 65

Summary: variable-width in / variable-width out queue needed
Product: Libre-SOC's first SoC Reporter: Luke Kenneth Casson Leighton <lkcl>
Component: Source CodeAssignee: Luke Kenneth Casson Leighton <lkcl>
Status: CONFIRMED ---    
Severity: enhancement CC: libre-soc-bugs
Priority: ---    
Version: unspecified   
Hardware: PC   
OS: Linux   
NLnet milestone: NLnet.2019.02.012 total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0 parent task for budget allocation:
child tasks for budget allocation: The table of payments (in EUR) for this task; TOML format:
Bug Depends on:    
Bug Blocks: 62    

Description Luke Kenneth Casson Leighton 2019-04-19 09:16:05 BST 
in many scenarios, data comes in at a different speed or bitrate from
the speed or bitwidth at which it goes out.  examples:

* UART handling.  data comes in bit-wise, goes out byte-wise
* SATA 8/10 checksum and handling.  data comes in bitwise, is checked, bytes-out
* Wishbone / AXI4 bridges: data comes in 64-bit, goes out 16-bit
* instruction buffer: data comes in on cache-line width, goes out 16/32/48/64

this latter is more complex in that the data needs to be inspected
intrusively in order to ascertain how much will go out.