| Summary: | TestIssuer does not terminate in svp64 mode test_issuer_svp64.py | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Luke Kenneth Casson Leighton <lkcl> |
| Component: | Source Code | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | CONFIRMED --- | ||
| Severity: | enhancement | CC: | cestrauss, libre-soc-bugs |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Linux | ||
| See Also: |
https://bugs.libre-soc.org/show_bug.cgi?id=737 https://bugs.libre-soc.org/show_bug.cgi?id=383 |
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| NLnet milestone: | --- | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
in commit f25faf58a3ed81 the test runner was converted to a new API which, instead of running single-step concurrently HDL-Simulator instruction 1, HDL-Simulator instruction 2, .... it is now HDL instruction 1, HDL instruction 2 ... followed separately by Simulator instruction 1, Simulator instruction 2 ... HDL in SVP64 is not correctly detecting a terminating condition, instead entering a permanent loop. test_runner.py: terminated = yield self.issuer.dbg.terminated_o this is never being set (in svp64 mode) and therefore the HDL simulation never terminates.