Bug 75

Summary: create an IEEE754 FP "add" pipeline
Product: Libre-SOC's first SoC Reporter: Luke Kenneth Casson Leighton <lkcl>
Component: ALU (including IEEE754 16/32/64-bit FPU)Assignee: Luke Kenneth Casson Leighton <lkcl>
Status: PAYMENTPENDING FIXED    
Severity: enhancement CC: libre-soc-bugs
Priority: ---    
Version: unspecified   
Hardware: PC   
OS: Linux   
NLnet milestone: NLnet.2019.02.012 total budget (EUR) for completion of task and all subtasks: 1500
budget (EUR) for this task, excluding subtasks' budget: 1500 parent task for budget allocation: 48
child tasks for budget allocation: The table of payments (in EUR) for this task; TOML format:
"lkcl"={amount=1500, paid=2019-06-04}
Bug Depends on:    
Bug Blocks: 48    

Description Luke Kenneth Casson Leighton 2019-04-26 21:35:30 BST
an IEEE754 FP pipelined "add" is needed which can do FP16/32/64