Bug 754

Summary:	stray instructions end up in -.csv
Product:	Libre-SOC's second ASIC	Reporter:	Jacob Lifshay <programmerjake>
Component:	source code	Assignee:	Luke Kenneth Casson Leighton <lkcl>
Status:	CONFIRMED ---
Severity:	normal	CC:	libre-soc-bugs
Priority:	---
Version:	unspecified
Hardware:	PC
OS:	Linux
See Also:	https://bugs.libre-soc.org/show_bug.cgi?id=745
NLnet milestone:	---	total budget (EUR) for completion of task and all subtasks:	0
budget (EUR) for this task, excluding subtasks' budget:	0	parent task for budget allocation:
child tasks for budget allocation:		The table of payments (in EUR) for this task; TOML format:

Description Jacob Lifshay 2021-12-10 20:42:57 GMT

https://bugs.libre-soc.org/show_bug.cgi?id=745#c32

> > While I'm at it, I become annoyed with constantly having -.csv 
> 
> erm...
> 
> > and sv_decode.vhdl 
> > be untracked files in openpower/isatables/
> > Should I add them to .gitignore or should I commit them?
> 
> ermmm...ermermerm....  these are actually important to have
> properly examined, lwzu for example is clearly a mistake.
> can you please raise a bugreport about them, to be investigated
> in the meantime i'll put something in sv_analysis.py
> (edit: please cross-ref this commit in the bugreport
> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=81c20b9e15d931ef58195644767a58944d933336)
> 
> insn,CONDITIONS,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
> dcbz,,0,EXTRA2,0,0,0,0,RA_OR_ZERO,RB,0,0,0,0,0
> lwzu,SVP64BREV,0,EXTRA2,0,0,0,0,RA_OR_ZERO,0,RC,RT,0,0,RA
> lbzu,SVP64BREV,0,EXTRA2,0,0,0,0,RA_OR_ZERO,0,RC,RT,0,0,RA
> lhzu,SVP64BREV,0,EXTRA2,0,0,0,0,RA_OR_ZERO,0,RC,RT,0,0,RA
> lhau,SVP64BREV,0,EXTRA2,0,0,0,0,RA_OR_ZERO,0,RC,RT,0,0,RA
> lfsu,SVP64BREV,0,EXTRA2,0,0,0,0,RA,0,RC,FRT,0,0,RA
> lfdu,SVP64BREV,0,EXTRA2,0,0,0,0,RA,0,RC,FRT,0,0,RA
> 1/6=mtfsb1,,0,EXTRA2,0,0,0,0,0,0,0,0,0,CR1,0
> 2/0=mcrfs,,0,EXTRA2,0,0,0,0,0,0,0,0,0,BF,0
> 2/6=mtfsb0,,0,EXTRA2,0,0,0,0,0,0,0,0,0,CR1,0
> 4/6=mtfsfi,,0,EXTRA2,0,0,0,0,0,0,0,0,0,CR1,0