Bug 777

Summary: Add / documentation / relicense Tercel QSPI XIP core
Product: Libre-SOC's first SoC Reporter: tpearson
Component: Source CodeAssignee: Luke Kenneth Casson Leighton <lkcl>
Status: RESOLVED FIXED    
Severity: enhancement CC: libre-soc-bugs
Priority: ---    
Version: unspecified   
Hardware: Other   
OS: Linux   
NLnet milestone: NLnet.2019.02.012 total budget (EUR) for completion of task and all subtasks: 1750
budget (EUR) for this task, excluding subtasks' budget: 1750 parent task for budget allocation: 50
child tasks for budget allocation: The table of payments (in EUR) for this task; TOML format:
tpearson={amount=1750, submitted=2022-02-26, paid=2022-03-03}

Description tpearson 2022-02-23 18:33:26 GMT 
- Added the Tercel QSPI XIP-capable core to the LibreSoC Microwatt tree
   - Reworked Microwatt to pull internal SPI core hooks out of main SoC
 - Enabled on ECP5-85 Arctic Tern boards
 - Documented core (initial datasheet)
 - Verified synthesis / PAR and resource usage
 - Relicensed as LGPLv3+