Bug 796

Summary: Tercel SPI PHY POR reset fails under certain conditions
Product: Libre-SOC's first SoC Reporter: tpearson
Component: Source CodeAssignee: Luke Kenneth Casson Leighton <lkcl>
Status: CONFIRMED ---    
Severity: normal CC: libre-soc-bugs
Priority: ---    
Version: unspecified   
Hardware: Other   
OS: Other   
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Description tpearson 2022-04-02 20:26:26 BST
Under specific conditions with a short (relative to SPI clock) power on reset pulse, the Tercel SPI controller PHY may fail to reset, leading to undefined behavior until an external reset is triggered.

This is fixed in GIT hash bf4f580 (microwatt).