Bug 808

Summary:	ICache module unconditionally accepts Wishbone ACK
Product:	Libre-SOC's first SoC	Reporter:	tpearson
Component:	Source Code	Assignee:	Luke Kenneth Casson Leighton <lkcl>
Status:	RESOLVED INVALID
Severity:	minor	CC:	libre-soc-bugs
Priority:	---
Version:	unspecified
Hardware:	Other
OS:	Other
See Also:	https://bugs.libre-soc.org/show_bug.cgi?id=807
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Description tpearson 2022-04-11 18:39:04 BST

The ICache module appears to unconditionally accept all ACKs from the connected Wishbone slave and treat them as valid data transfers, even if the bus is in a STALL state.

I am unclear as to whether this is intentional, but it does mask specific types of non-compliancy in connected peripherals, e.g. that seen in bug 807.

Comment 1 Luke Kenneth Casson Leighton 2022-04-11 19:16:23 BST

any chance if you could do a screenshot of gtkwave traces with arrows
pointing at where-it-goes-wrong?

with icache.py being an exact duplication of icache.vhdl this will
be a bug in microwatt as well.

Comment 2 tpearson 2022-04-11 19:18:54 BST

Sure, give me a bit to get the async bridges for #806 finished first.  They show the problem quite nicely with the fix for #807 reverted.

Comment 3 Luke Kenneth Casson Leighton 2022-04-16 18:13:07 BST

declaring this one invalid because WB3 classic master cannot drive WB4 pipe
slave.

WB4 Pipe stb *has* to be behind WB4 pipe ack (by at least 1 clock) where if
stall is set it will be longer than 1 clock.