Bug 81

Summary:	implement 6600-style "precise" out-of-order scoreboard
Product:	Libre-SOC's first SoC	Reporter:	Luke Kenneth Casson Leighton <lkcl>
Component:	Source Code	Assignee:	Luke Kenneth Casson Leighton <lkcl>
Status:	RESOLVED FIXED
Severity:	enhancement	CC:	libre-soc-bugs
Priority:	---
Version:	unspecified
Hardware:	PC
OS:	Linux
See Also:	http://bugs.libre-riscv.org/show_bug.cgi?id=276 https://bugs.libre-soc.org/show_bug.cgi?id=197
NLnet milestone:	NLnet.2019.02.012	total budget (EUR) for completion of task and all subtasks:	4100
budget (EUR) for this task, excluding subtasks' budget:	0	parent task for budget allocation:	191
child tasks for budget allocation:	86 94 95 292	The table of payments (in EUR) for this task; TOML format:
Bug Depends on:	87, 88, 92, 338, 86, 94, 95
Bug Blocks:	22
Attachments:	clarification of LD/ST dependency cell clarification of LD/ST Function Unit logic

Description Luke Kenneth Casson Leighton 2019-05-04 08:44:12 BST

first phase:

* research and documentation
* preliminary implementation (including minor unit tests)
* evaluation and addition of ALUs
* comprehensive unit test suite
* formal verification

second phase:

* addition of FP ALUs
* addition of LD/ST Matrix
* addition of branch prediction
* addition of exceptions / interrupts

(sub-phases for each: unit tests, formal verification)

third phase:

* addition of precise "nameless" Q-Table history
* addition of SIMD ALUs
* addition of vectorisation (multi-issue OoO elements)
* addition of "hierarchical cascade" (64/32/16/8-bit) hazards

(sub-phases for each: unit tests, formal verification)

Comment 1 Luke Kenneth Casson Leighton 2019-05-06 05:07:08 BST

discussion / links (edit as appropriate, add new links as-and-when)

* https://groups.google.com/a/groups.riscv.org/forum/#!topic/hw-dev/b4pPvlzBzu0

Comment 2 Luke Kenneth Casson Leighton 2019-05-06 05:11:17 BST

Created attachment 12 [details]
clarification of LD/ST dependency cell

WAR and RAW are unclocked SR-Latches

Comment 3 Luke Kenneth Casson Leighton 2019-05-06 06:47:16 BST

Created attachment 13 [details]
clarification of LD/ST Function Unit logic

SR Latches apparently don't like both inputs being ASSERTED,
seeking clarification from mitch on the use of a single SRLatch

Comment 4 Luke Kenneth Casson Leighton 2019-05-08 11:00:35 BST

first revision of modules from mitch alsup book chapters now created,
with a high-level exploratory unit test created, currently being
debugged.

it appears that there are combinatorial loops involving busy/issue
on SRLatches, which are being investigated.

a single "add", once a delay is added, seems to be successful.

Comment 5 Luke Kenneth Casson Leighton 2019-05-10 07:02:35 BST

https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/9nn4haAuAQAJ

https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/experiment/cscore.py;h=be085c51ad814c02c5446616168659767b6bdfd8;hb=1cc0064235ffaa9cea2439e2c9e92f5711b7dc1c

is now functional, and has been tested several times with up to 100 random
instructions.  caveats described in the above post to hw-dev.

Comment 6 Luke Kenneth Casson Leighton 2020-03-10 18:11:11 GMT

LDSTCompUnit basic unit test now works: two STs followed by two LDs will return the correct data from the LDs, and the ADD and ADD-immediate i've confirmed also work.

the next phase is to use these in the score6600.py experiment and see if
the "instructions" result in actual LDs and STs.

Comment 7 Luke Kenneth Casson Leighton 2020-03-10 21:00:17 GMT

managed to get LDSTCompUnit operational in score6600.py, needs more
investigation and checking, including more significant unit tests.