| Summary: | FPGA Simulation | ||
|---|---|---|---|
| Product: | Libre-SOC's second ASIC | Reporter: | Luke Kenneth Casson Leighton <lkcl> |
| Component: | Milestones | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | RESOLVED FIXED | ||
| Severity: | enhancement | CC: | libre-soc-bugs |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | Other | ||
| OS: | Linux | ||
| URL: | https://libre-soc.org/HDL_workflow/ls2/ | ||
| NLnet milestone: | NGI.POINTER.Gigabit.ASIC | total budget (EUR) for completion of task and all subtasks: | 12000 |
| budget (EUR) for this task, excluding subtasks' budget: | 12000 | parent task for budget allocation: | 814 |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: |
# viola paid
red={amount=12000, submitted=2022-06-20, paid=2022-07-09}
|
|
| Bug Depends on: | 803, 805, 811, 812, 801, 804, 806 | ||
| Bug Blocks: | 690, 814 | ||
|
Description
Luke Kenneth Casson Leighton
2022-04-16 18:08:12 BST
|