| Summary: | Adding wire RC to the layout extractor (Solstice) | ||
|---|---|---|---|
| Product: | Libre-SOC's second ASIC | Reporter: | Jean-Paul Chaput <Jean-Paul.Chaput> |
| Component: | source code | Assignee: | Jean-Paul Chaput <Jean-Paul.Chaput> |
| Status: | RESOLVED FIXED | ||
| Severity: | enhancement | CC: | libre-soc-bugs, lkcl |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Linux | ||
| NLnet milestone: | NLnet.2021-08-049.coriolis2 | total budget (EUR) for completion of task and all subtasks: | 3000 |
| budget (EUR) for this task, excluding subtasks' budget: | 3000 | parent task for budget allocation: | 748 |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
|
Description
Jean-Paul Chaput
2022-04-29 16:01:50 BST
|