Bug 825

Summary: Add a new parser/driver able to handle Verilog names
Product: Libre-SOC's second ASIC Reporter: Jean-Paul Chaput <Jean-Paul.Chaput>
Component: source codeAssignee: Jean-Paul Chaput <Jean-Paul.Chaput>
Status: RESOLVED FIXED    
Severity: enhancement CC: libre-soc-bugs, lkcl
Priority: ---    
Version: unspecified   
Hardware: PC   
OS: Linux   
NLnet milestone: NLnet.2021-08-049.coriolis2 total budget (EUR) for completion of task and all subtasks: 6000
budget (EUR) for this task, excluding subtasks' budget: 6000 parent task for budget allocation: 748
child tasks for budget allocation: The table of payments (in EUR) for this task; TOML format:

Description Jean-Paul Chaput 2022-04-29 16:15:34 BST 
Currently, Coriolis can only read/write netlist in:

* BLIF, which is completely obsolete and is used *only* because
  it was quicker than to develop a Verilog parser.

* VST, the Alliance VHDL subset, which cannot handle all the valid
  characters in Verilog so we must perform a name mangling which
  muddies the netlist.

To solve that, add a new parser driver so we can directly support
Verilog names. We should choose among the following candidates:

* Verilog (simplified version for netlist) for obvious reasons.
* RTLIL, as the native output format of Yosys, but not ideal for
  other ones.
* FIRRTL
  https://github.com/chipsalliance/firrtl/blob/master/spec/spec.pdf