Bug 827

Summary: 2RW SRAM cell design; 1RW SRAM cell improvement
Product: Libre-SOC's second ASIC Reporter: Staf Verhaegen <staf>
Component: source codeAssignee: Staf Verhaegen <staf>
Status: RESOLVED INVALID    
Severity: enhancement CC: libre-soc-bugs, lkcl
Priority: ---    
Version: unspecified   
Hardware: PC   
OS: Linux   
NLnet milestone: NGI.POINTER.Gigabit.ASIC total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0 parent task for budget allocation:
child tasks for budget allocation: The table of payments (in EUR) for this task; TOML format:
Bug Depends on:    
Bug Blocks: 690    

Description Staf Verhaegen 2022-05-02 14:09:05 BST 
For the Gigabit ASIC dual port 2RW SRAM blocks will be developed.
This task is for development of the 2RW SRAM cell. It consists of the design and layout of the cell.
Also the 1RW SRAM cell will be visited as likely the area can be reduced with w reduction of the transistors.