Bug 829

Summary:	Post-layout verification of ASIC SRAM blocks
Product:	Libre-SOC's second ASIC	Reporter:	Staf Verhaegen <staf>
Component:	source code	Assignee:	Staf Verhaegen <staf>
Status:	RESOLVED INVALID
Severity:	enhancement	CC:	libre-soc-bugs, lkcl
Priority:	---
Version:	unspecified
Hardware:	PC
OS:	Linux
NLnet milestone:	NGI.POINTER.Gigabit.ASIC	total budget (EUR) for completion of task and all subtasks:	0
budget (EUR) for this task, excluding subtasks' budget:	0	parent task for budget allocation:
child tasks for budget allocation:		The table of payments (in EUR) for this task; TOML format:
Bug Depends on:
Bug Blocks:	690

Description Staf Verhaegen 2022-05-02 14:29:54 BST

The blocks that will be on the router ASIC and generated by the compilers developed in bug #828 should be verified with simulation and (estimated) parasitics. This is for both the used 1RW and 2RW blocks.
Especially bigger block will need to be verified for race conditions on the internal signals due to the load on the nets.
The effort needed for this exercise will depend on the number of unique blocks and the size of the blocks.