| Summary: | Fix pseudo-code parser to correctly ignore html comments | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Jacob Lifshay <programmerjake> |
| Component: | Source Code | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | CONFIRMED --- | ||
| Severity: | major | CC: | libre-soc-bugs |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | Other | ||
| OS: | Linux | ||
| NLnet milestone: | --- | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
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Description
Jacob Lifshay
2022-05-03 10:50:30 BST
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=2b1d3614362d4f1a18d28d8d324b7f275a62f5bf should be sorted. (In reply to Luke Kenneth Casson Leighton from comment #1) > https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff; > h=2b1d3614362d4f1a18d28d8d324b7f275a62f5bf > > should be sorted. still broke: page svfixedarith madded /home/jacob/projects/libreriscv/openpower-isa/src/openpower/decoder/isa/svfixedarith.py madded <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below --> <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL --> <!-- bit 8 of EXTRA is set : RS.[s|v]=RC.[s|v] --> prod[0:127] <- (RA) * (RB) sum[0:127] <- EXTZ(RC) + prod RT <- sum[64:127] RS <- sum[0:63] form VA Fields(RA=(sig VA_RA), RB=(sig VA_RB), RC=(sig VA_RC), RT=(sig VA_RT), SHB=(sig VA_SHB), VRA=(sig VA_VRA), VRB=(sig VA_VRB), VRC=(sig VA_VRC), VRT=(sig VA_VRT), XO=(sig VA_XO)) Fields(RA=(sig VA_RA), RB=(sig VA_RB), RC=(sig VA_RC), RT=(sig VA_RT), SHB=(sig VA_SHB), VRA=(sig VA_VRA), VRB=(sig VA_VRB), VRC=(sig VA_VRC), VRT=(sig VA_VRT), XO=(sig VA_XO)) Traceback (most recent call last): File "/home/jacob/.virtualenvs/libre-riscv-venv/bin/pywriter", line 11, in <module> load_entry_point('libresoc-openpower-isa', 'console_scripts', 'pywriter')() File "/home/jacob/projects/libreriscv/openpower-isa/src/openpower/decoder/pseudo/pywriter.py", line 171, in pywriter isa.write_pysource(source) File "/home/jacob/projects/libreriscv/openpower-isa/src/openpower/decoder/pseudo/pywriter.py", line 80, in write_pysource pycode, rused = convert_to_python(pcode, d.form, incl_carry) File "/home/jacob/projects/libreriscv/openpower-isa/src/openpower/decoder/power_pseudo.py", line 275, in convert_to_python tree = gsc.compile(pcode, mode="exec", filename="string") File "/home/jacob/projects/libreriscv/openpower-isa/src/openpower/decoder/pseudo/parser.py", line 979, in compile tree = self.parser.parse(code) File "/home/jacob/projects/libreriscv/openpower-isa/src/openpower/decoder/pseudo/parser.py", line 949, in parse result = self.parser.parse(code, lexer=self.lexer, debug=self.debug) File "/home/jacob/.virtualenvs/libre-riscv-venv/lib/python3.8/site-packages/ply/yacc.py", line 333, in parse return self.parseopt_notrack(input, lexer, debug, tracking, tokenfunc) File "/home/jacob/.virtualenvs/libre-riscv-venv/lib/python3.8/site-packages/ply/yacc.py", line 1201, in parseopt_notrack tok = call_errorfunc(self.errorfunc, errtoken, self) File "/home/jacob/.virtualenvs/libre-riscv-venv/lib/python3.8/site-packages/ply/yacc.py", line 192, in call_errorfunc r = errorfunc(token) File "/home/jacob/projects/libreriscv/openpower-isa/src/openpower/decoder/pseudo/parser.py", line 920, in p_error raise SyntaxError(p) SyntaxError: LexToken(LT,'<',1,0) make: *** [Makefile:18: pywriter] Error 1 |