Bug 862

Summary:	setvl Vertical-First mode issues with predicates, extend setvl to 64 bit
Product:	Libre-SOC's first SoC	Reporter:	Luke Kenneth Casson Leighton <lkcl>
Component:	Specification	Assignee:	Luke Kenneth Casson Leighton <lkcl>
Status:	CONFIRMED ---
Severity:	enhancement	CC:	libre-soc-isa
Priority:	---
Version:	unspecified
Hardware:	Other
OS:	Linux
URL:	https://libre-soc.org/openpower/sv/setvl
See Also:	https://bugs.libre-soc.org/show_bug.cgi?id=568 https://bugs.libre-soc.org/show_bug.cgi?id=535 https://bugs.libre-soc.org/show_bug.cgi?id=587
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Description Luke Kenneth Casson Leighton 2022-06-17 19:09:03 BST

predicates in Horizontal-First Mode are loaded at the start of each instruction.
for Vertical-First this is a problem.

Comment 1 Luke Kenneth Casson Leighton 2022-06-17 19:45:02 BST

https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=6cac17aa4a16c30c337a26cb083138d5fbc0ef74

here was an idea of having a CTR reading mode.  VF mode needs some bits
to say which preficates are to be protected (made read-only).  therefore
swap vf with ct bit, and move vf mode to 24 bit RM.

then, add bits 4 for r3 r10 r30 CRf
then, allow CR Predicate to be selected starting
from CR16,CR32,CR48,CR64 (2 bits)

Comment 2 Luke Kenneth Casson Leighton 2022-06-18 10:24:58 BST

given that VF mode only uses a single bit this is fine.  that will be a single
CRf in CR Predication.