Bug 87

Summary:	investigate scoreboard global write pending change
Product:	Libre-SOC's first SoC	Reporter:	Luke Kenneth Casson Leighton <lkcl>
Component:	Source Code	Assignee:	Luke Kenneth Casson Leighton <lkcl>
Status:	CONFIRMED ---
Severity:	minor	CC:	libre-soc-bugs
Priority:	Lowest
Version:	unspecified
Hardware:	PC
OS:	Linux
NLnet milestone:	NLnet.2019.02.012	total budget (EUR) for completion of task and all subtasks:	0
budget (EUR) for this task, excluding subtasks' budget:	0	parent task for budget allocation:
child tasks for budget allocation:		The table of payments (in EUR) for this task; TOML format:
Bug Depends on:
Bug Blocks:	81
Attachments:	show invert on global write vector

Description Luke Kenneth Casson Leighton 2019-05-23 10:18:51 BST

Created attachment 16 [details]
show invert on global write vector

details:
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-May/001525.html

needs a thorough investigation: the global write pending vector might be
possible to invert and AND with the FU's read pending vector:

      Readable = 0;
      for(i=0; i < 32; i++)
          Readable |= ~global_INT_Write_Pending[i] & Int_Read_Pending[i];

this would stop the readable signal from going HI even on idle.

Comment 1 Luke Kenneth Casson Leighton 2019-05-25 21:27:00 BST

https://groups.google.com/d/msg/comp.arch/LXWtd1L9JoY/7P7yifihBQAJ

Multi-issue should begin with the current state of the Read reservations and 
of the write reservations (and the FU_busy). 

As each instruction is considered for issue, you take its read reservations 
and OR it onto the current read reservations, and likewise for the write 
reservations. 

Thus, by the time you decide to issue {1,2,3,4,5} you already HAVE the 
read and write reservations for that FU you are issuing into transitively 
through the whole set of issuing instructions. 

1-issue just uses the current read and write reservations 
2-issue uses the current for inst 1 and current OR inst 1 reservations for 
        inst 2. 
3-issue uses the current for inst 1 and current OR inst 1 reservations for 
        inst 2 and current OR inst 1&2 reservations for inst 3 
4-issue uses the current for inst 1 and current OR inst 1 reservations for 
        inst 2 and current OR inst 1&2 reservations for inst 3 and current 
        OR inst 1&2&3 for inst 4 
5-issue uses the current for inst 1 and current OR inst 1 reservations for 
        inst 2 and current OR inst 1&2 reservations for inst 3 and current 
        OR inst 1&2&3 for inst 4 and current OR inst 1&2&3&4 for inst 5 

Thus, 5-issue is only 1 gate <delay> harder than 1-issue over where one is 
keeping track of data and control flow dependencies.