Bug 888

Created attachment 185 [details]
Output PLL frequency versus time : plot of a typical power-off transient response of the designed PLL with Fref=20MHz

The displayed output of the PLL is a divided-by-two the frequency of the VCO and the multiplied-by-12 the frequency of the input reference.

I have succeeded to port the generator written for the PLL in 180nm TSMC technology to skywriter 130 technology. The new generator is based on the ngspice tool and python libraries, which makes it fully "open source". 

The generator based on Jupiter notebooks provides a working PLL ngspice netlist defined as a sub circuit, which is ready to be tested under different conditions (Vdd, input reference frequency, etc.). 

The developed design methodology is described in the attached documents. 

The netlist of one version of the generated PLL is given here. The full sources of the generator allowing one to generate netlists with different parameters are about to be provided on the GitHub of LIP6, the link will be given shortly.

(In reply to Dimitri Galayko from comment #2)
> I have succeeded to port the generator written for the PLL in 180nm TSMC
> technology to skywriter 130 technology. The new generator is based on the
> ngspice tool and python libraries, which makes it fully "open source". 

that's fantastic, a big deal.

> The generator based on Jupiter notebooks provides a working PLL ngspice
> netlist defined as a sub circuit, which is ready to be tested under
> different conditions (Vdd, input reference frequency, etc.). 

interesting approach, using jupiter.

> The developed design methodology is described in the attached documents. 

hm, some attachment types are limited, can you email them to me, i will
put them online rather than in the bugtracker PostgreSQL database

Created attachment 186 [details]
Output PLL frequency versus time : plot of a typical power-off transient response of the designed PLL with Fref=25 MHz

Different outputs of the divider are selected, yelling different multiples of the ref. frequency at the output.

To be done on the PLL:
 
-- The current reference generator (a CMOS quad or a bandgap). Some difficulties with the analog models of the transistors in the sky13O PDK delayed this implementation. The present model of the PLL uses an ideal current source instead. That should be fixed soon. 

-- Integration of ngspice and python: I used the shared library allowing one to manage the ngspice from a python code (https://pyspice.fabrice-salvaire.fr/releases/v1.3/api/PySpice/Spice/NgSpice/Shared.html).  That works pretty well, but poorly documented, and the netlist/simulations are very difficult to debug: the ngspice messages and errors are not displayed. Some effort is required from the community to provide a full console output of ngspice when running from a python code.

from professor galayko

Please find attached the three report files (to start from the file on PLL) describing the PLL design with their blocks.

One of the versions of the generated PLL, which works well and whose specs correspond to the design done for the first LibreSOC chip (tsmc180), but here implemented in sky130. The readme file provides information about how to simulate it.

In addition to these files, there are generators themselves (the notebooks), which will also be published on LIP6 GitHub, and which allows one to generate a PLL for a range of specifications. We will publish it on GitHub of LIP6, since, I believe, updates will be necessary. I would like to find a beta tester for all that.

full reports here 

https://ftp.libre-soc.org/ngi_pointer_888_lip6_sky130_pll.zip

while reading the report i noticed that in the charge pump pdf in figures 2 and 3 schematic of the cmos charge pump that M31 is missing the circle indicating it's a pmos transistor.

you may want to fix that.