| Summary: | Continue work on Atomics extension | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Jacob Lifshay <programmerjake> |
| Component: | Specification | Assignee: | Jacob Lifshay <programmerjake> |
| Status: | DEFERRED --- | ||
| Severity: | enhancement | CC: | libre-soc-isa, lkcl, programmerjake |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Linux | ||
| URL: | https://libre-soc.org/openpower/atomics | ||
| See Also: | https://bugs.libre-soc.org/show_bug.cgi?id=236 | ||
| NLnet milestone: | Future | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
| Bug Depends on: | 236 | ||
| Bug Blocks: | |||
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Description
Jacob Lifshay
2022-08-02 06:18:14 BST
I just thought of a way to add atomic ops that don't need memory model work: we simply define them in terms of the existing instruction sequences for the atomic ops. this also means they are trivially interoperable with all existing atomic ops. e.g. relaxed fetch_add is currently: https://rust.godbolt.org/z/eP974v3cf # addr in r3, addend in r4, result in r5 .LBB0_1: lbarx 5, 0, 3 add 6, 4, 5 stbcx. 6, 0, 3 bne 0, .LBB0_1 so amoadd r5, r4, r3 would be defined to be equivalent to the above code (except not modifying CR0 or r6) (In reply to Jacob Lifshay from comment #1) > I just thought of a way to add atomic ops that don't need memory model work: > we simply define them in terms of the existing instruction sequences for the > atomic ops. this saves us a lot of work and saves OPF and IBM a lot of work verifying the new instructions work in the memory model, the only problem is they may be slower than necessary for C++11's memory model. LLVM may be changing how it lowers relaxed loads to include a dummy branch: https://discourse.llvm.org/t/rfc-strengthen-relaxed-atomics-implementation-behind-mstrict-rlx-atomics-flag/74473 We should take the outcome of that into account when designing our atomic instructions. |