| Summary: | pysvp64dis: disassemble SVP64 instructions | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Dmitry Selyutin <ghostmansd> |
| Component: | Source Code | Assignee: | Dmitry Selyutin <ghostmansd> |
| Status: | RESOLVED FIXED | ||
| Severity: | enhancement | CC: | libre-soc-bugs, lkcl |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Linux | ||
| NLnet milestone: | NLNet.2019.10.042.Vulkan | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | 917 |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
| Bug Depends on: | |||
| Bug Blocks: | 917 | ||
|
Description
Dmitry Selyutin
2022-09-01 09:38:33 BST
Progress on SVP64 instructions: implemented decoding of possible modes except for branch mode. Now we select the modes properly (unless I made an error which is perfectly possible). In addition to information like for word instructions (https://bugs.libre-soc.org/show_bug.cgi?id=919#c5), I'm going to support verbose mode here too, and output all relevant bits (most importantly various fields). Just started implementing the verbose mode for SVP64-augmented instructions. Currently very similar to word instructions (in fact, most of the methods operate on the suffix).
40 0a 40 05 sv.add
14 6a e2 7e
spec
sv.add RT,RA,RB (OE=0 Rc=0)
binary
[0:8] 00000101
[8:16] 01000000
[16:24] 00001010
[24:32] 01000000
[32:40] 01111110
[40:48] 11100010
[48:56] 01101010
[56:64] 00010100
opcode
0x7c000214
mask
0xfc0007ff
RT
01010
[6, 7, 8, 9, 10]
RA
00000
[11, 12, 13, 14, 15]
RB
00001
[16, 17, 18, 19, 20]
OE
0
[21]
Rc
0
[31]
|