Bug 928

Summary:	ld/st with shift
Product:	Libre-SOC's first SoC	Reporter:	Jacob Lifshay <programmerjake>
Component:	Specification	Assignee:	Luke Kenneth Casson Leighton <lkcl>
Status:	CONFIRMED ---
Severity:	enhancement	CC:	libre-soc-isa
Priority:	---
Version:	unspecified
Hardware:	Other
OS:	Linux
See Also:	https://bugs.libre-soc.org/show_bug.cgi?id=585 https://bugs.libre-soc.org/show_bug.cgi?id=905
NLnet milestone:	NLnet.2022-08-051.OPF	total budget (EUR) for completion of task and all subtasks:	0
budget (EUR) for this task, excluding subtasks' budget:	0	parent task for budget allocation:
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Bug Depends on:
Bug Blocks:	952

Description Jacob Lifshay 2022-09-21 00:26:12 BST

couldn't find a bug for this, so making one.

ld/st with shift isn't very useful for rt = mem((ra << sh) + imm) unless imm is >25-bits or so, so instead i think the ops we'll want are (only listing loads here, stores are analogous):
rt = mem(pc + (rb << sh) + imm) -- can be encoded by ra=0

rt = mem(ra + (rb << sh) + imm)

we'll also want a way to enable bounds checking and base addr. addition for webassembly, so imho we reserve the max sh value (for 3-bit, that'd be sh=7) to enable wasm addressing mode instead of shifting. for details, see https://bugs.libre-soc.org/show_bug.cgi?id=585

we could alternatively reserve sh=0 for wasm, since that's redundant with the existing ld/st ops and that allows sh to reasonably be only 2 bits if we're low on space. imho reserving sh=0 seems like the best idea in retrospect.