| Summary: | add Cache-as-ram mode for boot | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Jacob Lifshay <programmerjake> |
| Component: | Specification | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | CONFIRMED --- | ||
| Severity: | enhancement | CC: | libre-soc-bugs |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | All | ||
| OS: | All | ||
| NLnet milestone: | --- | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
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Description
Jacob Lifshay
2019-06-05 08:29:01 BST
mitch writes: BTW, the way I solved this in my ISA/Architecture; is to define an "Allocated" bit in the PTEs (My architecture comes out of reset with the MMU turned on and paging enabled--there is actually no means to disable the MMU). The Allocated PTE bit tells the cache hierarchy that this line will not be migrated outside of the caches. The line can migrate up from L2 to L1 or migrate down from L1 to L2 but is not allowed to migrate farther out than L2. So I can now use the memory of the caches as a place to store data while DRAM gets initialized, and configured, counted, bundled, and handed over to the OS later boot processes. |