| Summary: | FP16 mul bug | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Luke Kenneth Casson Leighton <lkcl> |
| Component: | ALU (including IEEE754 16/32/64-bit FPU) | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | RESOLVED FIXED | ||
| Severity: | enhancement | CC: | libre-soc-bugs |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Linux | ||
| NLnet milestone: | --- | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
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Description
Luke Kenneth Casson Leighton
2019-06-16 13:42:27 BST
send 0 3 0xf73b 0x802e 0x2d32 recv 0 0x2d30 expected 0x2d32 fixed: was related to the normalisation phases being entirely missing. tiny numbers just above zero were entering the MUL phase with the mantissa not being '1' in the MSB. consequently the product was nowhere near accurate. fixed by shifting both A and B up so that the mantissa always has "1" in the MSB. |