Bug 986

Summary: SVP64 LD/ST format simplification
Product: Libre-SOC's first SoC Reporter: Luke Kenneth Casson Leighton <lkcl>
Component: SpecificationAssignee: Luke Kenneth Casson Leighton <lkcl>
Status: CONFIRMED ---    
Severity: enhancement CC: libre-soc-isa
Priority: ---    
Version: unspecified   
Hardware: PC   
OS: Linux   
URL: https://libre-soc.org/openpower/sv/ldst/
NLnet milestone: NLnet.2022-08-051.OPF total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0 parent task for budget allocation: 952
child tasks for budget allocation: The table of payments (in EUR) for this task; TOML format:
Bug Depends on:    
Bug Blocks: 952    

Description Luke Kenneth Casson Leighton 2022-12-11 15:47:17 GMT 
realisation after adding post-increment mode that LDST needs to be
redesigned:

* bit 0: post-increment
* bit 1: element-strided
* bit 2: Fault-First in LDST-Imm, SEA in LDST-Idx
* bit 3: dz
* bit 4: sz

this is a huge simplification but also removing modes that really
should be associated with Arithmetic/CRops, otherwise LDST becomes
CISC.

https://libre-soc.org/irclog/%23libre-soc.2022-12-10.log.html#t2022-12-10T11:29:38