Bug 41 - share 2x 32 bit FMUL pipeline stages to create a 64 bit FMUL
Summary: share 2x 32 bit FMUL pipeline stages to create a 64 bit FMUL
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: ALU (including IEEE754 16/32/64-bit FPU) (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks:
 
Reported: 2019-03-09 05:36 GMT by Luke Kenneth Casson Leighton
Modified: 2019-04-15 12:26 BST (History)
1 user (show)

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Description Luke Kenneth Casson Leighton 2019-03-09 05:36:11 GMT 
to save on gates, the idea is to share a pair of 32-bit multiply stages to create 64-bit results.

this will likely require that a 64-bit FMUL be a variable-length pipeline, carrying out a matrix of HI-word / LO-word 32-bit multiplies and summing them.  if any permutation of HI/LO-word is zero, the actual 32-32-bit multiply need not be performed.