Bug 42 - combine multiple IEEE754 module stages to reduce the pipeline length
Summary: combine multiple IEEE754 module stages to reduce the pipeline length
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: ALU (including IEEE754 16/32/64-bit FPU) (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks:
 
Reported: 2019-03-09 05:37 GMT by Luke Kenneth Casson Leighton
Modified: 2019-04-15 12:26 BST (History)
1 user (show)

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Description Luke Kenneth Casson Leighton 2019-03-09 05:37:29 GMT 
For example, there are at present separate rounding, correction and packing combinatorial blocks: these are simple enough that they can be chained into just the one pipeline phase.  In this way it will be possible to get the total number of pipeline stages down to only 4 (for both the ADD and the MUL).