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Bug 1179 depends on 9 bugs:
view as bug list-
1179:
implement spec changes, rewrite SVP64 spec as a "actual inclusion in Power ISA".
[CONFIRMED; assigned to lkcl]
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1056:
questions and feedback (v2) on OPF RFC ls010 (Simple-V Zero-Overhead Loop Prefix Subsystem)
[RESOLVED FIXED; assigned to lkcl]
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995:
align SVP64 instructions
[CONFIRMED; assigned to ghostmansd]
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1047:
SVP64 LD/ST Data-Dependent Fail-First providing linked-list walking
[IN_PROGRESS; assigned to lkcl]
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1080:
allowing LD/ST-Update to select individual regsters needed
[CONFIRMED; assigned to lkcl]
(*)
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1176:
implement CR-Based (not CR *FIELD* based) SVP64 in ISACaller (sv.mcrxr, sv.mtcr etc)
[CONFIRMED; assigned to lkcl]
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1045:
OPF ISA External RFC ls010 - SVP64 Zero-Overhead Loop Prefix System
[RESOLVED FIXED; assigned to lkcl]
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1084:
interesting pysvp64dis bug (in power_insn.py)
[RESOLVED FIXED; assigned to ghostmansd]
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1161:
EXTRA2/3 algorithm likely inconsistent with EXTRA2 tables causing PowerDecoder2 and insndb to disagree on scalar EXTRA2 register encoding for >=r32
[RESOLVED FIXED; assigned to programmerjake]
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995:
align SVP64 instructions
[CONFIRMED; assigned to ghostmansd]
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1056:
questions and feedback (v2) on OPF RFC ls010 (Simple-V Zero-Overhead Loop Prefix Subsystem)
[RESOLVED FIXED; assigned to lkcl]
Bug 1179 does not block any bugs.
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