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Bug 204 depends on 11 bugs:

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•    204: Transition from symbolic to real Cell Library for 180nm layout [RESOLVED FIXED; assigned to staf]
  •    199: Layout using coriolis2 main core, 180nm [RESOLVED FIXED; assigned to Jean-Paul.Chaput]
    •    528: parameter needed in coriolis2 to specify individually which clocks are to have a Clock Tree [CONFIRMED; assigned to Jean-Paul.Chaput]
    •    200: IEEE754 FPU Coriolis2 layout [RESOLVED FIXED; assigned to lkcl]
    •    502: determine SRAM block size and implement it [RESOLVED FIXED; assigned to staf]
      •    591: Create yosys external cell wrapper for use by coriolis - DFF-SRAM block and Staf-SRAM blocks [RESOLVED FIXED; assigned to lkcl]
    •    506: 8x VDD VSS pins needed in ioring [RESOLVED FIXED; assigned to Jean-Paul.Chaput]
    •    507: ls180 asic needs an ioring, pads need defining and connecting [RESOLVED FIXED; assigned to Jean-Paul.Chaput]
      •    506: 8x VDD VSS pins needed in ioring [RESOLVED FIXED; assigned to Jean-Paul.Chaput] (*)
    •    508: decide package size and pin allocation for 180nm ASIC [RESOLVED FIXED; assigned to lkcl]
    •    521: small example using JTAG for testing coriolis2 new multi clock plugin [RESOLVED FIXED; assigned to lkcl]
    •    526: create dry-run 180nm GDS-II files for IMEC [RESOLVED FIXED; assigned to lkcl]
    •    620: post-layout simulation needed using cocotb [RESOLVED FIXED; assigned to staf]
  •    200: IEEE754 FPU Coriolis2 layout [RESOLVED FIXED; assigned to lkcl] (*)

Bug 204 blocks 2 bugs:

view as bug list

•    204: Transition from symbolic to real Cell Library for 180nm layout [RESOLVED FIXED; assigned to staf]
  •    138: NLNet 2019 Coriolis2 Layout proposal 2019-10-029 [RESOLVED FIXED; assigned to lkcl]
    •    938: All NLnet and NGI Grant Milestones [CONFIRMED; assigned to lkcl]

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