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Bug 22 depends on 57 bugs:
view as bug list-
22:
FPGA proof-of-concept test needed
[CONFIRMED; assigned to lkcl]
-
2:
Define and find hard macros for all Shakti M-Class Interfaces
[CONFIRMED; assigned to lkcl]
-
1:
I2C Interface
[CONFIRMED; assigned to lkcl]
-
3:
I2S interface
[CONFIRMED; assigned to lkcl]
-
4:
FlexBus Interface
[CONFIRMED; assigned to lkcl]
-
5:
RGB/TTL Interface
[CONFIRMED; assigned to lkcl]
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6:
SPI interface needed
[CONFIRMED; assigned to lkcl]
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7:
SD/MMC and eMMC interface needed
[CONFIRMED; assigned to lkcl]
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8:
Pinmux needed
[CONFIRMED; assigned to lkcl]
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24:
pinmux memory map
[IN_PROGRESS; assigned to lkcl]
-
25:
pinmux generate c header files
[CONFIRMED; assigned to lkcl]
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26:
pinmux default mux values
[IN_PROGRESS; assigned to lkcl]
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27:
pinmux synchroniser clocks
[CONFIRMED; assigned to lkcl]
-
30:
ULPI / UTMI needed into pinmux for code-generation
[CONFIRMED; assigned to lkcl]
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31:
need diff pair pin on pinmux
[CONFIRMED; assigned to lkcl]
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33:
pinmux verification of rules etc.
[CONFIRMED; assigned to lkcl]
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34:
pinmux add sdram interface
[IN_PROGRESS; assigned to lkcl]
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35:
pinmux add vme peripheral
[CONFIRMED; assigned to lkcl]
-
20:
pinmux needs to auto-generate bsv Makefile
[RESOLVED FIXED; assigned to lkcl]
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28:
pinmux dedicated peripherals code-gen needed
[RESOLVED FIXED; assigned to lkcl]
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50:
nmigen pinmux
[RESOLVED FIXED; assigned to lkcl]
-
846:
Pinmux Pinspec Interconnect Auto-Generation
[CONFIRMED; assigned to andy.miroshnikov]
-
746:
I2C needs an Open Drain IO Pad
[RESOLVED FIXED; assigned to staf]
-
750:
Convert pinmux gpio, jtag-block bitmap diagrams to svg vector
[RESOLVED FIXED; assigned to veerakumar.r]
-
762:
Peripheral Pin Muxing Development
[RESOLVED FIXED; assigned to andy.miroshnikov]
(*)
-
763:
Work on I/O Core Pad JTAG Tests
[RESOLVED FIXED; assigned to lkcl]
-
764:
Documentation of I/O Core/Pad JTAG Tests
[RESOLVED FIXED; assigned to andy.miroshnikov]
-
846:
Pinmux Pinspec Interconnect Auto-Generation
[CONFIRMED; assigned to andy.miroshnikov]
-
24:
pinmux memory map
[IN_PROGRESS; assigned to lkcl]
-
9:
RGMII (Gigabit Ethernet) Interface
[CONFIRMED; assigned to lkcl]
-
10:
AXI Bridge Interface
[CONFIRMED; assigned to lkcl]
-
11:
Wishbone Interface / Bridge
[CONFIRMED; assigned to lkcl]
-
12:
AC97 Audio Interface
[CONFIRMED; assigned to lkcl]
-
13:
PWM Interface needed
[CONFIRMED; assigned to lkcl]
-
14:
EINT interface needed (PLIC)
[CONFIRMED; assigned to lkcl]
-
15:
GPIO interface needed
[CONFIRMED; assigned to lkcl]
-
17:
IOMMU needed
[CONFIRMED; assigned to lkcl]
-
18:
PDM audio needed
[CONFIRMED; assigned to lkcl]
-
21:
LPDDR3/LPDDR4 needed
[CONFIRMED; assigned to lkcl]
-
1:
I2C Interface
[CONFIRMED; assigned to lkcl]
-
206:
Implement branch prediction
[CONFIRMED; assigned to lkcl]
-
81:
implement 6600-style "precise" out-of-order scoreboard
[RESOLVED FIXED; assigned to lkcl]
-
87:
investigate scoreboard global write pending change
[CONFIRMED; assigned to lkcl]
-
88:
investigate multi-issue (superscalar)
[CONFIRMED; assigned to lkcl]
-
92:
Implement in order instruction retire refcounting
[CONFIRMED; assigned to lkcl]
-
338:
CompUnitALU needs go_die to be wired to ALU shadow mask
[CONFIRMED; assigned to lkcl]
-
86:
6600-style preliminary investigation
[PAYMENTPENDING FIXED; assigned to lkcl]
-
94:
implement load/store memory dependency matrix
[RESOLVED FIXED; assigned to lkcl]
-
95:
implement shadowing for use in precise exceptions, branch speculation, predication and WaW ordering
[PAYMENTPENDING FIXED; assigned to lkcl]
-
87:
investigate scoreboard global write pending change
[CONFIRMED; assigned to lkcl]
-
186:
Create decoder for SOC: Power ISA
[RESOLVED FIXED; assigned to lkcl]
-
211:
formal proof of PowerDecoder stage2 needed
[CONFIRMED; assigned to lkcl]
-
189:
Create partitioned right shift using the existing partitioned left shift
[PAYMENTPENDING FIXED; assigned to mtnolan2640]
-
261:
power_enums.py to read SPRs from sprs.csv
[RESOLVED FIXED; assigned to lkcl]
-
271:
SigDecode in power_fields has extra spurious fields
[RESOLVED FIXED; assigned to mtnolan2640]
-
211:
formal proof of PowerDecoder stage2 needed
[CONFIRMED; assigned to lkcl]
-
412:
set up litex for peripherals and linking to core
[PAYMENTPENDING FIXED; assigned to lkcl]
-
2:
Define and find hard macros for all Shakti M-Class Interfaces
[CONFIRMED; assigned to lkcl]
Bug 22 blocks 7 bugs:
view as bug list-
22:
FPGA proof-of-concept test needed
[CONFIRMED; assigned to lkcl]
-
191:
NLNet 2019 Core Proposal 2019-02-012
[RESOLVED FIXED; assigned to lkcl]
-
383:
Complete first functional POWER9 Core
[RESOLVED FIXED; assigned to lkcl]
-
443:
Bperm optimization
[DEFERRED; assigned to lkcl]
-
698:
ls180 ASIC test tasks
[CONFIRMED; assigned to lkcl]
-
961:
NLnet 2022 Libre-SOC "ongoing" milestone 2022-08-107 (approved, MoU signed, waiting countersignature)
[CONFIRMED; assigned to lkcl]
-
175:
NLNet 2019 Wishbone proposal 2019-10-043
[RESOLVED FIXED; assigned to lkcl]
-
443:
Bperm optimization
[DEFERRED; assigned to lkcl]
-
191:
NLNet 2019 Core Proposal 2019-02-012
[RESOLVED FIXED; assigned to lkcl]
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