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Bug 383 depends on 71 open bugs:
view as bug list-
383:
Complete first functional POWER9 Core
[RESOLVED FIXED; assigned to lkcl]
-
11:
Wishbone Interface / Bridge
[CONFIRMED; assigned to lkcl]
-
22:
FPGA proof-of-concept test needed
[CONFIRMED; assigned to lkcl]
-
2:
Define and find hard macros for all Shakti M-Class Interfaces
[CONFIRMED; assigned to lkcl]
-
1:
I2C Interface
[CONFIRMED; assigned to lkcl]
-
3:
I2S interface
[CONFIRMED; assigned to lkcl]
-
4:
FlexBus Interface
[CONFIRMED; assigned to lkcl]
-
5:
RGB/TTL Interface
[CONFIRMED; assigned to lkcl]
-
6:
SPI interface needed
[CONFIRMED; assigned to lkcl]
-
7:
SD/MMC and eMMC interface needed
[CONFIRMED; assigned to lkcl]
-
8:
Pinmux needed
[CONFIRMED; assigned to lkcl]
-
24:
pinmux memory map
[IN_PROGRESS; assigned to lkcl]
-
25:
pinmux generate c header files
[CONFIRMED; assigned to lkcl]
-
26:
pinmux default mux values
[IN_PROGRESS; assigned to lkcl]
-
27:
pinmux synchroniser clocks
[CONFIRMED; assigned to lkcl]
-
30:
ULPI / UTMI needed into pinmux for code-generation
[CONFIRMED; assigned to lkcl]
-
31:
need diff pair pin on pinmux
[CONFIRMED; assigned to lkcl]
-
33:
pinmux verification of rules etc.
[CONFIRMED; assigned to lkcl]
-
34:
pinmux add sdram interface
[IN_PROGRESS; assigned to lkcl]
-
35:
pinmux add vme peripheral
[CONFIRMED; assigned to lkcl]
-
24:
pinmux memory map
[IN_PROGRESS; assigned to lkcl]
-
9:
RGMII (Gigabit Ethernet) Interface
[CONFIRMED; assigned to lkcl]
-
10:
AXI Bridge Interface
[CONFIRMED; assigned to lkcl]
-
11:
Wishbone Interface / Bridge
[CONFIRMED; assigned to lkcl]
(*)
-
12:
AC97 Audio Interface
[CONFIRMED; assigned to lkcl]
-
13:
PWM Interface needed
[CONFIRMED; assigned to lkcl]
-
14:
EINT interface needed (PLIC)
[CONFIRMED; assigned to lkcl]
-
15:
GPIO interface needed
[CONFIRMED; assigned to lkcl]
-
17:
IOMMU needed
[CONFIRMED; assigned to lkcl]
-
18:
PDM audio needed
[CONFIRMED; assigned to lkcl]
-
21:
LPDDR3/LPDDR4 needed
[CONFIRMED; assigned to lkcl]
-
1:
I2C Interface
[CONFIRMED; assigned to lkcl]
-
206:
Implement branch prediction
[CONFIRMED; assigned to lkcl]
-
2:
Define and find hard macros for all Shakti M-Class Interfaces
[CONFIRMED; assigned to lkcl]
-
155:
a PLL is needed for the SoC
[CONFIRMED; assigned to dimitri.galayko]
-
216:
LOAD STORE buffer needed
[CONFIRMED; assigned to lkcl]
-
304:
Define minimum viable interface set for 180nm ASIC
[CONFIRMED; assigned to lkcl]
-
318:
fix LDSTCompUnit
[CONFIRMED; assigned to cestrauss]
-
321:
BUG: Running ltp on a pipeline gives warnings about loops
[CONFIRMED; assigned to lkcl]
-
336:
ALU CompUnit needs to recognise that RA (src1) can be zero
[CONFIRMED; assigned to cestrauss]
-
350:
LDSTCompUnit also needs to support zeroing on RA
[CONFIRMED; assigned to cestrauss]
-
352:
virtual (dependency-tracked) regfile (cache) needed
[CONFIRMED; assigned to lkcl]
-
356:
fu POWER9 pipeline unit tests need to test RA=0
[CONFIRMED; assigned to lkcl]
-
359:
cut down on wires between decode and function units
[CONFIRMED; assigned to lkcl]
-
361:
all test_pipe_caller.py needs RA=0 tests
[CONFIRMED; assigned to lkcl]
-
390:
ISACaller get_assembly_name() not identifying mtocrf / mtcrf correctly
[CONFIRMED; assigned to lkcl]
-
396:
create simulator PowerISA div/mod functions
[IN_PROGRESS; assigned to programmerjake]
-
397:
design and discuss user-tag flags in wishbone to provide phase 1 / 2 "speculative" memory accesses
[CONFIRMED; assigned to lkcl]
-
410:
Design Bus Protocol suitable for speculative execution
[CONFIRMED; assigned to lkcl]
-
415:
miscellaneous POWER9 instructions needed: OP_NOP, ATTN, ILLEGAL and unit tests
[CONFIRMED; assigned to lkcl]
-
423:
st*cx. needs to be able to update CR0
[CONFIRMED; assigned to lkcl]
-
424:
need to respect 32/64 bit mode
[CONFIRMED; assigned to lkcl]
-
427:
LDST cache-inhibit instructions needed (l*cix, st*cix)
[CONFIRMED; assigned to lkcl]
-
428:
create separate MSR regfile
[CONFIRMED; assigned to lkcl]
-
432:
mulld pseudocode overflow calculation incorrect
[IN_PROGRESS; assigned to lkcl]
-
434:
remove mask_wid from TestMemPspec
[CONFIRMED; assigned to lkcl]
-
447:
document DMI registers and format for use in microwatt and libre-soc
[CONFIRMED; assigned to lkcl]
-
448:
MUL pipeline unit tests
[IN_PROGRESS; assigned to lkcl]
-
462:
add integer POWER9 MAC operation
[CONFIRMED; assigned to lkcl]
-
465:
add LoadStore error and exception handling via PortInterface
[CONFIRMED; assigned to lkcl]
(*)
-
470:
convert code using LoadStoreInterface to PortInterface
[CONFIRMED; assigned to lkcl]
-
479:
need to check mulhwo. on IBM POWER9 hardware
[CONFIRMED; assigned to lkcl]
-
484:
Write VHDL to expose CR and XER from Microwatt so single-stepping is possible
[CONFIRMED; assigned to lkcl]
-
486:
Script and document the setup and installation of microwatt dependency on the wiki-HDL_workflow page
[CONFIRMED; assigned to lkcl]
-
489:
PowerDecoder2 notes
[CONFIRMED; assigned to lkcl]
-
498:
JTAG ECP5 "tap" needed
[CONFIRMED; assigned to lkcl]
-
512:
use m.submodules["...%d"] = mod instead of setattr
[CONFIRMED; assigned to lkcl]
-
514:
review ls180 reset connections
[CONFIRMED; assigned to lkcl]
-
515:
confirm that it is possible to upload into SRAM via JTAG (firmware upload / processor start script)
[CONFIRMED; assigned to lkcl]
-
522:
opcode csv file discrepancies
[CONFIRMED; assigned to lkcl]
-
525:
add dcbz pseudocode
[CONFIRMED; assigned to lkcl]
-
528:
parameter needed in coriolis2 to specify individually which clocks are to have a Clock Tree
[CONFIRMED; assigned to Jean-Paul.Chaput]
-
629:
TRAP pipeline unit test failures
[CONFIRMED; assigned to lkcl]
-
11:
Wishbone Interface / Bridge
[CONFIRMED; assigned to lkcl]
Bug 383 blocks 4 open bugs:
view as bug list-
383:
Complete first functional POWER9 Core
[RESOLVED FIXED; assigned to lkcl]
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