| Max Depth: |
Bug 961 depends on 204 bugs:
view as bug list-
961:
NLnet 2022 Libre-SOC "ongoing" milestone 2022-08-107 (approved, MoU signed, waiting countersignature)
[CONFIRMED; assigned to lkcl]
-
737:
in-order single-issue Power ISA 3.0 core
[CONFIRMED; assigned to cestrauss]
-
726:
Additional core_stop check after Execute breaks single-stepping
[CONFIRMED; assigned to cestrauss]
-
747:
verify that instructions that write to the same register twice are correctly decoded as illegal/trap
[CONFIRMED; assigned to lkcl]
-
749:
in-order core needs to be out-of-order (6600)
[CONFIRMED; assigned to lkcl]
-
1094:
insndb instruction database visitor-walker is needed
[RESOLVED FIXED; assigned to ghostmansd]
-
726:
Additional core_stop check after Execute breaks single-stepping
[CONFIRMED; assigned to cestrauss]
-
990:
gram needs changes to work on the orangecrab
[CONFIRMED; assigned to libre-soc]
-
995:
align SVP64 instructions
[CONFIRMED; assigned to ghostmansd]
-
1003:
instruction database continuation and binutils, SVP64
[CONFIRMED; assigned to ghostmansd]
-
1081:
pay special attention to stfiwx UNDEFINED behaviour
[CONFIRMED; assigned to lkcl]
-
1086:
ls2 verilator sim - setting up chroot and documentation
[CONFIRMED; assigned to andy.miroshnikov]
-
1127:
Generating a Libre-SOC Microwatt-compatible core with SVP64
[CONFIRMED; assigned to andy.miroshnikov]
-
1176:
implement CR-Based (not CR *FIELD* based) SVP64 in ISACaller (sv.mcrxr, sv.mtcr etc)
[CONFIRMED; assigned to lkcl]
-
383:
Complete first functional POWER9 Core
[RESOLVED FIXED; assigned to lkcl]
-
11:
Wishbone Interface / Bridge
[CONFIRMED; assigned to lkcl]
-
22:
FPGA proof-of-concept test needed
[CONFIRMED; assigned to lkcl]
-
2:
Define and find hard macros for all Shakti M-Class Interfaces
[CONFIRMED; assigned to lkcl]
-
1:
I2C Interface
[CONFIRMED; assigned to lkcl]
-
3:
I2S interface
[CONFIRMED; assigned to lkcl]
-
4:
FlexBus Interface
[CONFIRMED; assigned to lkcl]
-
5:
RGB/TTL Interface
[CONFIRMED; assigned to lkcl]
-
6:
SPI interface needed
[CONFIRMED; assigned to lkcl]
-
7:
SD/MMC and eMMC interface needed
[CONFIRMED; assigned to lkcl]
-
8:
Pinmux needed
[CONFIRMED; assigned to lkcl]
-
24:
pinmux memory map
[IN_PROGRESS; assigned to lkcl]
-
25:
pinmux generate c header files
[CONFIRMED; assigned to lkcl]
-
26:
pinmux default mux values
[IN_PROGRESS; assigned to lkcl]
-
27:
pinmux synchroniser clocks
[CONFIRMED; assigned to lkcl]
-
30:
ULPI / UTMI needed into pinmux for code-generation
[CONFIRMED; assigned to lkcl]
-
31:
need diff pair pin on pinmux
[CONFIRMED; assigned to lkcl]
-
33:
pinmux verification of rules etc.
[CONFIRMED; assigned to lkcl]
-
34:
pinmux add sdram interface
[IN_PROGRESS; assigned to lkcl]
-
35:
pinmux add vme peripheral
[CONFIRMED; assigned to lkcl]
-
20:
pinmux needs to auto-generate bsv Makefile
[RESOLVED FIXED; assigned to lkcl]
-
28:
pinmux dedicated peripherals code-gen needed
[RESOLVED FIXED; assigned to lkcl]
-
50:
nmigen pinmux
[RESOLVED FIXED; assigned to lkcl]
-
846:
Pinmux Pinspec Interconnect Auto-Generation
[CONFIRMED; assigned to andy.miroshnikov]
-
746:
I2C needs an Open Drain IO Pad
[RESOLVED FIXED; assigned to staf]
-
750:
Convert pinmux gpio, jtag-block bitmap diagrams to svg vector
[RESOLVED FIXED; assigned to veerakumar.r]
-
762:
Peripheral Pin Muxing Development
[RESOLVED FIXED; assigned to andy.miroshnikov]
(*)
-
763:
Work on I/O Core Pad JTAG Tests
[RESOLVED FIXED; assigned to lkcl]
-
764:
Documentation of I/O Core/Pad JTAG Tests
[RESOLVED FIXED; assigned to andy.miroshnikov]
-
846:
Pinmux Pinspec Interconnect Auto-Generation
[CONFIRMED; assigned to andy.miroshnikov]
-
24:
pinmux memory map
[IN_PROGRESS; assigned to lkcl]
-
9:
RGMII (Gigabit Ethernet) Interface
[CONFIRMED; assigned to lkcl]
-
10:
AXI Bridge Interface
[CONFIRMED; assigned to lkcl]
-
11:
Wishbone Interface / Bridge
[CONFIRMED; assigned to lkcl]
(*)
-
12:
AC97 Audio Interface
[CONFIRMED; assigned to lkcl]
-
13:
PWM Interface needed
[CONFIRMED; assigned to lkcl]
-
14:
EINT interface needed (PLIC)
[CONFIRMED; assigned to lkcl]
-
15:
GPIO interface needed
[CONFIRMED; assigned to lkcl]
-
17:
IOMMU needed
[CONFIRMED; assigned to lkcl]
-
18:
PDM audio needed
[CONFIRMED; assigned to lkcl]
-
21:
LPDDR3/LPDDR4 needed
[CONFIRMED; assigned to lkcl]
-
1:
I2C Interface
[CONFIRMED; assigned to lkcl]
-
206:
Implement branch prediction
[CONFIRMED; assigned to lkcl]
-
81:
implement 6600-style "precise" out-of-order scoreboard
[RESOLVED FIXED; assigned to lkcl]
-
87:
investigate scoreboard global write pending change
[CONFIRMED; assigned to lkcl]
-
88:
investigate multi-issue (superscalar)
[CONFIRMED; assigned to lkcl]
-
92:
Implement in order instruction retire refcounting
[CONFIRMED; assigned to lkcl]
-
338:
CompUnitALU needs go_die to be wired to ALU shadow mask
[CONFIRMED; assigned to lkcl]
-
86:
6600-style preliminary investigation
[PAYMENTPENDING FIXED; assigned to lkcl]
-
94:
implement load/store memory dependency matrix
[RESOLVED FIXED; assigned to lkcl]
-
95:
implement shadowing for use in precise exceptions, branch speculation, predication and WaW ordering
[PAYMENTPENDING FIXED; assigned to lkcl]
-
87:
investigate scoreboard global write pending change
[CONFIRMED; assigned to lkcl]
-
186:
Create decoder for SOC: Power ISA
[RESOLVED FIXED; assigned to lkcl]
-
211:
formal proof of PowerDecoder stage2 needed
[CONFIRMED; assigned to lkcl]
-
189:
Create partitioned right shift using the existing partitioned left shift
[PAYMENTPENDING FIXED; assigned to mtnolan2640]
-
261:
power_enums.py to read SPRs from sprs.csv
[RESOLVED FIXED; assigned to lkcl]
-
271:
SigDecode in power_fields has extra spurious fields
[RESOLVED FIXED; assigned to mtnolan2640]
-
211:
formal proof of PowerDecoder stage2 needed
[CONFIRMED; assigned to lkcl]
-
412:
set up litex for peripherals and linking to core
[PAYMENTPENDING FIXED; assigned to lkcl]
-
2:
Define and find hard macros for all Shakti M-Class Interfaces
[CONFIRMED; assigned to lkcl]
-
155:
a PLL is needed for the SoC
[CONFIRMED; assigned to dimitri.galayko]
-
216:
LOAD STORE buffer needed
[CONFIRMED; assigned to lkcl]
-
304:
Define minimum viable interface set for 180nm ASIC
[CONFIRMED; assigned to lkcl]
-
318:
fix LDSTCompUnit
[CONFIRMED; assigned to cestrauss]
-
321:
BUG: Running ltp on a pipeline gives warnings about loops
[CONFIRMED; assigned to lkcl]
-
336:
ALU CompUnit needs to recognise that RA (src1) can be zero
[CONFIRMED; assigned to cestrauss]
-
350:
LDSTCompUnit also needs to support zeroing on RA
[CONFIRMED; assigned to cestrauss]
-
352:
virtual (dependency-tracked) regfile (cache) needed
[CONFIRMED; assigned to lkcl]
-
356:
fu POWER9 pipeline unit tests need to test RA=0
[CONFIRMED; assigned to lkcl]
-
359:
cut down on wires between decode and function units
[CONFIRMED; assigned to lkcl]
-
361:
all test_pipe_caller.py needs RA=0 tests
[CONFIRMED; assigned to lkcl]
-
390:
ISACaller get_assembly_name() not identifying mtocrf / mtcrf correctly
[CONFIRMED; assigned to lkcl]
-
396:
create simulator PowerISA div/mod functions
[IN_PROGRESS; assigned to programmerjake]
-
397:
design and discuss user-tag flags in wishbone to provide phase 1 / 2 "speculative" memory accesses
[CONFIRMED; assigned to lkcl]
-
410:
Design Bus Protocol suitable for speculative execution
[CONFIRMED; assigned to lkcl]
-
415:
miscellaneous POWER9 instructions needed: OP_NOP, ATTN, ILLEGAL and unit tests
[CONFIRMED; assigned to lkcl]
-
423:
st*cx. needs to be able to update CR0
[CONFIRMED; assigned to lkcl]
-
424:
need to respect 32/64 bit mode
[CONFIRMED; assigned to lkcl]
-
427:
LDST cache-inhibit instructions needed (l*cix, st*cix)
[CONFIRMED; assigned to lkcl]
-
428:
create separate MSR regfile
[CONFIRMED; assigned to lkcl]
-
432:
mulld pseudocode overflow calculation incorrect
[IN_PROGRESS; assigned to lkcl]
-
434:
remove mask_wid from TestMemPspec
[CONFIRMED; assigned to lkcl]
-
447:
document DMI registers and format for use in microwatt and libre-soc
[CONFIRMED; assigned to lkcl]
(*)
-
448:
MUL pipeline unit tests
[IN_PROGRESS; assigned to lkcl]
-
462:
add integer POWER9 MAC operation
[CONFIRMED; assigned to lkcl]
-
465:
add LoadStore error and exception handling via PortInterface
[CONFIRMED; assigned to lkcl]
(*)
-
470:
convert code using LoadStoreInterface to PortInterface
[CONFIRMED; assigned to lkcl]
-
479:
need to check mulhwo. on IBM POWER9 hardware
[CONFIRMED; assigned to lkcl]
-
484:
Write VHDL to expose CR and XER from Microwatt so single-stepping is possible
[CONFIRMED; assigned to lkcl]
-
486:
Script and document the setup and installation of microwatt dependency on the wiki-HDL_workflow page
[CONFIRMED; assigned to lkcl]
-
489:
PowerDecoder2 notes
[CONFIRMED; assigned to lkcl]
-
498:
JTAG ECP5 "tap" needed
[CONFIRMED; assigned to lkcl]
-
512:
use m.submodules["...%d"] = mod instead of setattr
[CONFIRMED; assigned to lkcl]
-
514:
review ls180 reset connections
[CONFIRMED; assigned to lkcl]
-
515:
confirm that it is possible to upload into SRAM via JTAG (firmware upload / processor start script)
[CONFIRMED; assigned to lkcl]
-
522:
opcode csv file discrepancies
[CONFIRMED; assigned to lkcl]
-
525:
add dcbz pseudocode
[CONFIRMED; assigned to lkcl]
-
528:
parameter needed in coriolis2 to specify individually which clocks are to have a Clock Tree
[CONFIRMED; assigned to Jean-Paul.Chaput]
-
629:
TRAP pipeline unit test failures
[CONFIRMED; assigned to lkcl]
-
186:
Create decoder for SOC: Power ISA
[RESOLVED FIXED; assigned to lkcl]
(*)
-
302:
create a list of exception types for LD/ST operations in POWER
[RESOLVED DUPLICATE; assigned to lkcl]
-
305:
Create Pipelined ALU similar to alu_hier.py
[RESOLVED FIXED; assigned to mtnolan2640]
-
319:
POWER9 setting carry (and other) XER flags
[CONFIRMED; assigned to mtnolan2640]
-
361:
all test_pipe_caller.py needs RA=0 tests
[CONFIRMED; assigned to lkcl]
(*)
-
306:
Formal Correctness Proof for ALU pipeline
[RESOLVED FIXED; assigned to kc5tja]
-
334:
POWER decode A=zero needs to be set as a flag in Execute1Type
[RESOLVED FIXED; assigned to lkcl]
(*)
-
337:
Convention for register outputs in *OutputData structures is to use "Data"
[RESOLVED FIXED; assigned to lkcl]
(*)
-
358:
new MCU-ALU test picked up RC / OE / CR handling issue
[RESOLVED FIXED; assigned to mtnolan2640]
-
360:
move RS to 1st or 2nd operand in CSV files
[RESOLVED FIXED; assigned to lkcl]
-
369:
missing XER SO/OV/32 check in test_pipe_caller.py
[RESOLVED FIXED; assigned to lkcl]
-
319:
POWER9 setting carry (and other) XER flags
[CONFIRMED; assigned to mtnolan2640]
-
313:
Create Branch Pipeline for POWER9
[RESOLVED FIXED; assigned to mtnolan2640]
-
314:
Create POWER9 Condition Register pipeline
[RESOLVED FIXED; assigned to mtnolan2640]
-
356:
fu POWER9 pipeline unit tests need to test RA=0
[CONFIRMED; assigned to lkcl]
(*)
-
332:
Formal correctness proof needed for CR pipeline
[RESOLVED FIXED; assigned to mtnolan2640]
-
333:
investigate why CR pipeline code took 100% CPU and locked up generating ILANG
[RESOLVED FIXED; assigned to lkcl]
-
360:
move RS to 1st or 2nd operand in CSV files
[RESOLVED FIXED; assigned to lkcl]
(*)
-
356:
fu POWER9 pipeline unit tests need to test RA=0
[CONFIRMED; assigned to lkcl]
-
315:
SPR Pipeline needed
[RESOLVED DUPLICATE; assigned to lkcl]
-
323:
create POWER9 MUL pipeline
[RESOLVED FIXED; assigned to programmerjake]
-
356:
fu POWER9 pipeline unit tests need to test RA=0
[CONFIRMED; assigned to lkcl]
(*)
-
432:
mulld pseudocode overflow calculation incorrect
[IN_PROGRESS; assigned to lkcl]
(*)
-
448:
MUL pipeline unit tests
[IN_PROGRESS; assigned to lkcl]
(*)
-
419:
MUL pipeline formal proof needed
[RESOLVED FIXED; assigned to kc5tja]
-
356:
fu POWER9 pipeline unit tests need to test RA=0
[CONFIRMED; assigned to lkcl]
-
324:
create POWER DIV pipeline
[RESOLVED FIXED; assigned to programmerjake]
-
356:
fu POWER9 pipeline unit tests need to test RA=0
[CONFIRMED; assigned to lkcl]
(*)
-
396:
create simulator PowerISA div/mod functions
[IN_PROGRESS; assigned to programmerjake]
(*)
-
413:
DIV "trial" blocks are too large
[CONFIRMED; assigned to lkcl]
-
420:
DIV pipeline formal correctness proof needed
[CONFIRMED; assigned to lkcl]
-
425:
DIV overflow not being calculated correctly
[CONFIRMED; assigned to programmerjake]
-
437:
div test cases coordinated across different software/hdl
[CONFIRMED; assigned to lkcl]
-
438:
add caching/memoization to soc.simulator.program.Program
[CONFIRMED; assigned to programmerjake]
-
439:
generated op_divde appears to be incorrect
[CONFIRMED; assigned to programmerjake]
-
433:
building pia (power instruction analyser) needs to be documented
[RESOLVED FIXED; assigned to programmerjake]
-
449:
FU unit tests checking output one cycle too late
[RESOLVED FIXED; assigned to lkcl]
-
471:
bug in modsd DIV FSM
[RESOLVED FIXED; assigned to programmerjake]
-
356:
fu POWER9 pipeline unit tests need to test RA=0
[CONFIRMED; assigned to lkcl]
-
325:
create POWER9 TRAP pipeline
[RESOLVED FIXED; assigned to kc5tja]
-
330:
create POWER9 Logic Pipeline
[RESOLVED FIXED; assigned to mtnolan2640]
-
356:
fu POWER9 pipeline unit tests need to test RA=0
[CONFIRMED; assigned to lkcl]
(*)
-
361:
all test_pipe_caller.py needs RA=0 tests
[CONFIRMED; assigned to lkcl]
(*)
-
331:
Formal Correctness Proof for LOGICAL pipeline
[RESOLVED FIXED; assigned to lkcl]
-
360:
move RS to 1st or 2nd operand in CSV files
[RESOLVED FIXED; assigned to lkcl]
(*)
-
356:
fu POWER9 pipeline unit tests need to test RA=0
[CONFIRMED; assigned to lkcl]
-
339:
create POWER9 ROTATE (SHIFTROT) pipeline
[RESOLVED FIXED; assigned to mtnolan2640]
-
356:
fu POWER9 pipeline unit tests need to test RA=0
[CONFIRMED; assigned to lkcl]
(*)
-
361:
all test_pipe_caller.py needs RA=0 tests
[CONFIRMED; assigned to lkcl]
(*)
-
340:
formal proof of POWER9 SHIFTROT pipeline needed
[PAYMENTPENDING FIXED; assigned to programmerjake]
-
360:
move RS to 1st or 2nd operand in CSV files
[RESOLVED FIXED; assigned to lkcl]
(*)
-
369:
missing XER SO/OV/32 check in test_pipe_caller.py
[RESOLVED FIXED; assigned to lkcl]
(*)
-
356:
fu POWER9 pipeline unit tests need to test RA=0
[CONFIRMED; assigned to lkcl]
-
344:
missing mtmsr and mfsprd
[RESOLVED FIXED; assigned to lkcl]
-
345:
define POWER9 regfiles
[RESOLVED FIXED; assigned to lkcl]
-
346:
simplified test link between compunits and regfile
[RESOLVED FIXED; assigned to lkcl]
-
348:
POWER9 SPR pipeline needed
[RESOLVED FIXED; assigned to lkcl]
-
356:
fu POWER9 pipeline unit tests need to test RA=0
[CONFIRMED; assigned to lkcl]
(*)
-
481:
SPR pipeline forgot to use full_xer
[CONFIRMED; assigned to lkcl]
-
344:
missing mtmsr and mfsprd
[RESOLVED FIXED; assigned to lkcl]
(*)
-
418:
SPR pipeline formal correctness proof needed
[RESOLVED FIXED; assigned to kc5tja]
(*)
-
356:
fu POWER9 pipeline unit tests need to test RA=0
[CONFIRMED; assigned to lkcl]
-
349:
privileged-instruction decoding function needed
[RESOLVED FIXED; assigned to lkcl]
-
351:
create a "block" (mass) regfile port (read and write) onto an array-based regfile
[RESOLVED FIXED; assigned to lkcl]
(*)
-
382:
nmigen wishbone Memory (SRAM) object needed
[RESOLVED FIXED; assigned to lkcl]
-
393:
Hook up augmented-Wishbone Memory Bus to LDSTCompUnit (via PortInterface)
[RESOLVED FIXED; assigned to lkcl]
-
407:
XICS interrupt controller is needed
[RESOLVED FIXED; assigned to lkcl]
-
409:
deal with illegal instruction in simulator and hardware
[RESOLVED FIXED; assigned to lkcl]
-
412:
set up litex for peripherals and linking to core
[PAYMENTPENDING FIXED; assigned to lkcl]
(*)
-
414:
debug port needed (JTAG, other frontend)
[PAYMENTPENDING FIXED; assigned to lkcl]
(*)
-
416:
dec and tb POWER9 SPRs needed
[RESOLVED FIXED; assigned to lkcl]
-
418:
SPR pipeline formal correctness proof needed
[RESOLVED FIXED; assigned to kc5tja]
(*)
-
426:
LDST sign-extension support needed
[RESOLVED FIXED; assigned to lkcl]
-
435:
PC and MSR need to be in the "state" (Decode2Execute1Type)
[RESOLVED FIXED; assigned to lkcl]
(*)
-
441:
Avoid unit tests that depend on other unit tests being run first
[RESOLVED FIXED; assigned to programmerjake]
-
454:
Create "subset instruction decoders" that are *inside* mul0, *inside* alu0 and so on
[RESOLVED DUPLICATE; assigned to lkcl]
-
463:
python based cycle accurate POWER9 simulator
[RESOLVED FIXED; assigned to lkcl]
-
468:
wishbone downconverter needed
[RESOLVED FIXED; assigned to lkcl]
(*)
-
469:
Create D-cache from microwatt dcache.vhdl
[RESOLVED FIXED; assigned to lkcl]
-
471:
bug in modsd DIV FSM
[RESOLVED FIXED; assigned to programmerjake]
(*)
-
476:
addme ALU pipeline bug
[RESOLVED FIXED; assigned to lkcl]
-
478:
MFOCR and MCROF need to be one-hot
[RESOLVED FIXED; assigned to lkcl]
-
482:
mul ok and ov must not be unconditionally set
[RESOLVED FIXED; assigned to lkcl]
(*)
-
485:
Create I-Cache from microwatt icache.vhdl
[RESOLVED FIXED; assigned to lkcl]
-
490:
Complete peripheral set including litex for first functional OpenPOWER Core (ls180)
[RESOLVED FIXED; assigned to lkcl]
-
491:
MMU Function Unit needed
[RESOLVED FIXED; assigned to lkcl]
-
525:
add dcbz pseudocode
[CONFIRMED; assigned to lkcl]
(*)
-
636:
exceptions, predication and zeroing masks need to be added to Function Unit context
[CONFIRMED; assigned to lkcl]
-
450:
Create MMU from microwatt mmu.vhdl
[RESOLVED FIXED; assigned to lkcl]
(*)
-
469:
Create D-cache from microwatt dcache.vhdl
[RESOLVED FIXED; assigned to lkcl]
(*)
-
485:
Create I-Cache from microwatt icache.vhdl
[RESOLVED FIXED; assigned to lkcl]
(*)
-
756:
LDST PortInterface is not using MSR.DR for virtual mode
[RESOLVED FIXED; assigned to lkcl]
-
525:
add dcbz pseudocode
[CONFIRMED; assigned to lkcl]
-
492:
losing Elaboratables in div fsm.py
[RESOLVED FIXED; assigned to programmerjake]
-
493:
DMI JTAG TAP needed
[RESOLVED FIXED; assigned to colepoirier]
(*)
-
497:
use of pia is not being properly maintained and now the unit tests don't work
[RESOLVED INVALID; assigned to programmerjake]
-
502:
determine SRAM block size and implement it
[RESOLVED FIXED; assigned to staf]
(*)
-
508:
decide package size and pin allocation for 180nm ASIC
[RESOLVED FIXED; assigned to lkcl]
(*)
-
510:
check for combinatorial path through DIV FSM
[RESOLVED FIXED; assigned to lkcl]
-
511:
Add a test of IO pins to debug/test/test_jtag_tap.py
[RESOLVED FIXED; assigned to colepoirier]
-
513:
nmutil.extend.exts not being used in modsw
[RESOLVED FIXED; assigned to programmerjake]
-
516:
rldicl unit test failure
[RESOLVED FIXED; assigned to lkcl]
-
517:
Define JTAG pins and set up with litex for ulx3s85f
[RESOLVED FIXED; assigned to lkcl]
-
518:
Define JTAG pins and set up with litex for versa_ecp5
[RESOLVED DUPLICATE; assigned to colepoirier]
-
519:
Get output from ulx3s serial port to show up in minicom
[RESOLVED FIXED; assigned to colepoirier]
-
520:
Need a way to disable WB interface in core in case it gets stuck active
[RESOLVED FIXED; assigned to lkcl]
-
542:
miscategorised opcodes
[RESOLVED FIXED; assigned to lkcl]
-
580:
PowerDecoder needs to redirect MMU SPRs to the MMU
[RESOLVED FIXED; assigned to libre-soc]
-
591:
Create yosys external cell wrapper for use by coriolis - DFF-SRAM block and Staf-SRAM blocks
[RESOLVED FIXED; assigned to lkcl]
(*)
-
605:
Extend ECP5_FPGA wiki page with JTAG testing/boot procedure for Libre-SOC test chip
[RESOLVED FIXED; assigned to lkcl]
-
606:
PowerDecoder2 move DecodeCRIn/Out
[RESOLVED FIXED; assigned to lkcl]
-
11:
Wishbone Interface / Bridge
[CONFIRMED; assigned to lkcl]
-
988:
XLEN OPF ISA WG RFC ls005
[RESOLVED FIXED; assigned to lkcl]
-
999:
SFFS Operating System Porting
[RESOLVED FIXED; assigned to sadoon]
-
1004:
FPGA bring up for platform definitions
[RESOLVED FIXED; assigned to cestrauss]
-
1073:
Microwatt verilator sim - setting up chroot and documentation
[RESOLVED FIXED; assigned to andy.miroshnikov]
(*)
-
1093:
Fix "GPR-or-zero" in binutils and openpower-isa
[RESOLVED FIXED; assigned to ghostmansd]
-
1126:
How to document new bugs/issues
[RESOLVED FIXED; assigned to andy.miroshnikov]
-
1210:
sv.bc branching to incorrect address in Vertical-First mode
[RESOLVED FIXED; assigned to programmerjake]
-
737:
in-order single-issue Power ISA 3.0 core
[CONFIRMED; assigned to cestrauss]
Bug 961 blocks one bug:
view as bug list-
961:
NLnet 2022 Libre-SOC "ongoing" milestone 2022-08-107 (approved, MoU signed, waiting countersignature)
[CONFIRMED; assigned to lkcl]
| Max Depth: |