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Bug 961 depends on 12 open bugs:
view as bug list-
961:
NLnet 2022 Libre-SOC "ongoing" milestone 2022-08-107 (approved, MoU signed, waiting countersignature)
[CONFIRMED; assigned to lkcl]
-
737:
in-order single-issue Power ISA 3.0 core
[CONFIRMED; assigned to cestrauss]
-
726:
Additional core_stop check after Execute breaks single-stepping
[CONFIRMED; assigned to cestrauss]
-
747:
verify that instructions that write to the same register twice are correctly decoded as illegal/trap
[CONFIRMED; assigned to lkcl]
-
749:
in-order core needs to be out-of-order (6600)
[CONFIRMED; assigned to lkcl]
-
726:
Additional core_stop check after Execute breaks single-stepping
[CONFIRMED; assigned to cestrauss]
-
990:
gram needs changes to work on the orangecrab
[CONFIRMED; assigned to libre-soc]
-
995:
align SVP64 instructions
[CONFIRMED; assigned to ghostmansd]
-
1003:
instruction database continuation and binutils, SVP64
[CONFIRMED; assigned to ghostmansd]
-
1081:
pay special attention to stfiwx UNDEFINED behaviour
[CONFIRMED; assigned to lkcl]
-
1086:
ls2 verilator sim - setting up chroot and documentation
[CONFIRMED; assigned to andy.miroshnikov]
-
1127:
Generating a Libre-SOC Microwatt-compatible core with SVP64
[CONFIRMED; assigned to andy.miroshnikov]
-
1176:
implement CR-Based (not CR *FIELD* based) SVP64 in ISACaller (sv.mcrxr, sv.mtcr etc)
[CONFIRMED; assigned to lkcl]
-
737:
in-order single-issue Power ISA 3.0 core
[CONFIRMED; assigned to cestrauss]
Bug 961 blocks one open bug:
view as bug list-
961:
NLnet 2022 Libre-SOC "ongoing" milestone 2022-08-107 (approved, MoU signed, waiting countersignature)
[CONFIRMED; assigned to lkcl]
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